Originally Posted by David Heath (Post 1448761)

In reality it's more complicated than you infer, owing to the necessity to avoid interline twitter. Scanning a chip for interlace means that lines have to be summed, but differently for different fields. Hence the lines of an even field may formed from chip lines 1+2, 3+4, 5+6 etc, the lines of an odd field from 2+3, 4+5, 6+7 etc. This reduces twitter, but also reduces vertical resolution compared to progressive scanning.