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April 7th, 2011, 02:01 PM | #1 |
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Let's design a chip for HDTV and 4K2K cameras
Start with a 4:3 chip that can contain a 16:9 window.
H and V pixel counts must be divisible by 32 and 16. Obviously counts must be EVEN. Allow enough "extra" pixels to support debayering. Assume the "extra" factor is 86%. The chip would have 12.98M pixels from 4160 columns by 3120 rows. In HDTV mode, the 16:9 window would be 4160 by 2340 pixels. 1) Every other column and row would be skipped during read-out which gets you 2080 by 1170 pixels. Column and rows are skipped to drop the read-out data by a factor of 4X to enable the chip to run at 60Hz. After debayering you get 1934 by 1088 pixels which are encoded as 1920x1080. A total of about 2MPs. 2) No skipping is needed with this super fast chip, so 2080 by 1170 pixels are debayered and scaled to 1920x1080. 3) In some modes, skipping is used and in other modes it is not used. I point this out because I have seen a reference to "All Scan" mode. Column and rows may need to be skipped/discarded to enable the DSP to handle the data load coming from the chip. It's all a matter of clock rate, power consumption, and the ability to remove heat. Sony may not wish to fully describe these matters. In 4K2K mode, you have 4160 columns prior to debayering and 3868 after. Of which we need 3840. In 4K2K mode, you skip the top 390 and the bottom 390 of the chip's 3120 rows. This leaves 2340 rows prior to debayering and 2160 lines after. This is a 16:9 image. The 3840 and 2160 pixels are recorded, which is about 8.29MP. This is the future of cameras. Now, let's look back at the 12.98MP number. Does this number sound familiar? If you read Allan Robert's paper on the F3 his estimate of the Sony chip's pixel count is 12.96MP Hmmm! If he's correct, and my math is correct, it is certainly possible Sony has designed a chip that can be used first to support HDTV. But, when paired with a chip "like" the JVC GigaBrid, 8.29MP from the chip can be passed though the DSP and into an encoder thereby giving us a 4K2K camera. In fact, JVC already has demoed such a camera, but using a small sensor rather than a large sensor. Could JVC show-up at NAB with a big chip camera using the GigaBrid DSP and using a Sony chip? PS: Obviously 13MP is the EFFECTIVE pixel count. The GROSS pixel count could be from 14MP to 16MP. Which supports my feeling the "Super35" F3 sensor may be Sony's 16MP A55 chip.
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April 7th, 2011, 02:19 PM | #2 |
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Re: Let's design a chip for HDTV and 4K2K cameras
The HD-DPM+ sensor from Grass Valley does a similar thing.. It's a 2/3th inch sensor, with 1920 pixels horizontally and 4320 "sub pixels" vertically.
When it needs to operate in 1080 mode it reads out the 4320 sub pixels in groups of 4 (= 1080), so you get a native 1920x1080 resolution. When it needs to operate in 720 mode it reads out the 4320 sub pixels in groups of 6 (=720) so you get a native 1920x720 resolution. For the LDK8000 it doesn't change the aspect ratio. However on the old SD LDK10/20/100/200/300/400/500 series camera they used a similar system, where they had a 4:3 native sensor, which was read out in a similar way to the LDK8000. However there they used a way so that both 4:3 and 16:9 had the same amount of lines, because of the way they read out the lines. For the Viper they used a system like on the SD system, but on a native 16:9 HD sensor. They read it out for 2,35:1 in a way that they lost no resolution when switching the camera. It sounds like a complicated system and as I understood it is pretty expensive.. LDK8000 sheet, read page 2 at the top for more info about the CCD readout: http://www.creativevideo.co.uk/pdf/t...%20ldk8000.pdf |
April 22nd, 2011, 04:29 PM | #3 |
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Re: Let's design a chip for HDTV and 4K2K cameras
You are right -- other cameras have used switchable modes to obtain different outputs by organizing photosite samples in different ways.
Since nobody even tried to post how a dual mode chip could work -- I have posted an example of how. http://www.dvinfo.net/forum/sony-xdc...econciled.html
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April 27th, 2011, 10:51 PM | #4 |
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Re: Let's design a chip for HDTV and 4K2K cameras
Although the entire(http://www.dvinfo.net/forum/sony-xdc...econciled.html) thread was deleted, one of my points was that the F3/FS100 chip is an S35 version of the APS-C chip used in the A55. In the thread I stated that the reason why Sony was not be releasing the full specs. on the F3/FS100 chip, is that they are waiting for another camera to be released, but it was delayed by the events in Japan.
That camera appears to be the NEX-3C. One point made in NEX-3C pre-release buzz is this, "Rumor has it Sony originally intended to announce both cameras earlier in the month, but plans were delayed in the wake of the catastrophic earthquake in Japan."
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April 28th, 2011, 02:40 AM | #5 |
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Re: Let's design a chip for HDTV and 4K2K cameras
Sorry, the thread was deleted.
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